Discussion:
RTL8169S/8110S not supported on 4.0_STABLE?
(too old to reply)
Brad du Plessis
2008-03-06 13:07:49 UTC
Permalink
Hi all,

Originally I'd sent this to port-i386, but maybe someone here can help me.

I've got a Gigabyte motherboard with a Realtek onboard NIC and an
ifconfig shows the MAC to be all zeros.

Relevant dmesg at boot:

/netbsd: re0 at pci2 dev 0 function 0pci_mem_find: void region
/netbsd: : RealTek 8168B/8111B PCIe Gigabit Ethernet (rev. 0x02)
/netbsd: re0: interrupting at ioapic0 pin 17 (irq 10)
/netbsd: re0: Unknown revision (0x3c000000)
/netbsd: re0: Ethernet address 00:00:00:00:00:00
/netbsd: re0: using 256 tx descriptors
/netbsd: rgephy0 at re0 phy 7: RTL8169S/8110S 1000BASE-T media
interface, rev. 2
/netbsd: rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX,
1000baseT, 1000baseT-FDX, auto

and then later:

/netbsd: re0: PHY write reg 0 <- 8000 failed
/netbsd: re0: PHY write reg 1f <- 1 failed
/netbsd: re0: PHY write reg 9 <- 273a failed
/netbsd: re0: PHY write reg e <- 7bfb failed
/netbsd: re0: PHY write reg 1b <- 841e failed


It works with a cross-over CAT5 cable so it looks like it just may be
the probing of the MAC address. Has anyone got a patch to fix this?


Many thanks,
Brad


--
Posted automagically by a mail2news gateway at muc.de e.V.
Please direct questions, flames, donations, etc. to news-***@muc.de
Jonathan A. Kollasch
2008-03-06 15:35:16 UTC
Permalink
Post by Brad du Plessis
Hi all,
Originally I'd sent this to port-i386, but maybe someone here can help me.
I've got a Gigabyte motherboard with a Realtek onboard NIC and an ifconfig
shows the MAC to be all zeros.
/netbsd: re0 at pci2 dev 0 function 0pci_mem_find: void region
/netbsd: : RealTek 8168B/8111B PCIe Gigabit Ethernet (rev. 0x02)
/netbsd: re0: interrupting at ioapic0 pin 17 (irq 10)
/netbsd: re0: Unknown revision (0x3c000000)
This is probably a problem.

I however can't find reference to this 0x3c version in FreeBSD
or OpenBSD re(4), but I did find a reference in Realtek's version
of the FreeBSD driver.

But, no, I don't have a patch.

Jonathan Kollasch
Brad du Plessis
2008-03-07 12:48:41 UTC
Permalink
Post by Jonathan A. Kollasch
Post by Brad du Plessis
Hi all,
Originally I'd sent this to port-i386, but maybe someone here can help me.
I've got a Gigabyte motherboard with a Realtek onboard NIC and an ifconfig
shows the MAC to be all zeros.
/netbsd: re0 at pci2 dev 0 function 0pci_mem_find: void region
/netbsd: : RealTek 8168B/8111B PCIe Gigabit Ethernet (rev. 0x02)
/netbsd: re0: interrupting at ioapic0 pin 17 (irq 10)
/netbsd: re0: Unknown revision (0x3c000000)
This is probably a problem.
I however can't find reference to this 0x3c version in FreeBSD
or OpenBSD re(4), but I did find a reference in Realtek's version
of the FreeBSD driver.
But, no, I don't have a patch.
Can anything be deduced from the fact that the manual as well as the
print on the chip itself says that this is an 8111C while dmesg says
8111B? Would the 8111C use the same rtl8169 driver?

Thanks,
Brad


--
Posted automagically by a mail2news gateway at muc.de e.V.
Please direct questions, flames, donations, etc. to news-***@muc.de
Izumi Tsutsui
2008-03-13 15:03:37 UTC
Permalink
Post by Brad du Plessis
Can anything be deduced from the fact that the manual as well as the
print on the chip itself says that this is an 8111C while dmesg says
8111B?
Realtek uses the same PCI device ID for those chips,
and we use the ID to print device names.
Probably we could use device revision to distingush variants,
but there is no info about it.
Post by Brad du Plessis
Would the 8111C use the same rtl8169 driver?
Well, we need chip's manual to answer it.
In the sane design, the chip should have a differnt ID
if it requires a completely different driver.
(though minor quirks could be handled in the same driver)

Anyway, could you try the attached (untested) patch?
rgephy part is taken from FreeBSD, and some of values
are taken from RealTek's driver. Other changes (eeprom etc.)
are by my random guess.
---
Izumi Tsutsui



Index: dev/ic/rtl8169.c
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/rtl8169.c,v
retrieving revision 1.96
diff -u -r1.96 rtl8169.c
--- dev/ic/rtl8169.c 7 Feb 2008 01:21:54 -0000 1.96
+++ dev/ic/rtl8169.c 13 Mar 2008 14:48:33 -0000
@@ -590,7 +590,9 @@
/* Revision of 8169/8169S/8110s in bits 30..26, 23 */
hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV;
/* These rev numbers are taken from Realtek's driver */
- if ( hwrev == RTK_HWREV_8100E_SPIN2) {
+ if ( hwrev == RTK_HWREV_8168C) {
+ sc->sc_rev = 16;
+ } else if (hwrev == RTK_HWREV_8100E_SPIN2) {
sc->sc_rev = 15;
} else if (hwrev == RTK_HWREV_8100E) {
sc->sc_rev = 14;
@@ -1748,6 +1750,13 @@

DELAY(10000);

+ if (sc->sc_rev == 16) {
+ /* magic values for 8168C from Realtek driver */
+ CSR_WRITE_4(sc, RTK_CSIDR, 0x27000000);
+ CSR_WRITE_4(sc, RTK_CSIAR, 0x800087C0);
+
+ CSR_WRITE_1(sc, 0xD1, 0x38);
+ }
/*
* Init our MAC address. Even though the chipset
* documentation doesn't mention it, we need to enter "Config
@@ -1865,13 +1874,20 @@
* For 8169 gigE NICs, set the max allowed RX packet
* size so we can receive jumbo frames.
*/
- CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383);
+ if (sc->sc_rev != 16)
+ CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383);
+ else
+ CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 0x05EF);
}

if (sc->re_testmode)
return 0;

- CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD);
+ if (sc->sc_rev != 16)
+ CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD);
+ else
+ /* from Realtek driver for 8168C */
+ CSR_WRITE_1(sc, RTK_CFG1, 0);

ifp->if_flags |= IFF_RUNNING;
ifp->if_flags &= ~IFF_OACTIVE;
Index: dev/ic/rtl81x9.c
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/rtl81x9.c,v
retrieving revision 1.81
diff -u -r1.81 rtl81x9.c
--- dev/ic/rtl81x9.c 19 Jan 2008 22:10:17 -0000 1.81
+++ dev/ic/rtl81x9.c 13 Mar 2008 14:48:33 -0000
@@ -165,7 +165,7 @@
CSR_WRITE_1(sc, RTK_EECMD, \
CSR_READ_1(sc, RTK_EECMD) & ~(x))

-#define EE_DELAY() DELAY(100)
+#define EE_DELAY() DELAY(150)

#define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN)

@@ -209,6 +209,7 @@
CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM);
EE_DELAY();
EE_SET(RTK_EE_SEL);
+ EE_DELAY();

/*
* Send address of word we want to read.
Index: dev/ic/rtl81x9reg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/ic/rtl81x9reg.h,v
retrieving revision 1.29
diff -u -r1.29 rtl81x9reg.h
--- dev/ic/rtl81x9reg.h 6 Feb 2008 22:51:02 -0000 1.29
+++ dev/ic/rtl81x9reg.h 13 Mar 2008 14:48:34 -0000
@@ -88,6 +88,9 @@
/* 005F reserved */
#define RTK_TXSTAT_ALL 0x0060 /* TX status of all descriptors */

+#define RTK_CSIDR 0x0064
+#define RTK_CSIAR 0x0068
+
/* Direct PHY access registers only available on 8139 */
#define RTK_BMCR 0x0062 /* PHY basic mode control */
#define RTK_BMSR 0x0064 /* PHY basic mode status */
@@ -161,6 +164,7 @@
#define RTK_HWREV_8168_SPIN2 0x38000000
#define RTK_HWREV_8168_SPIN3 0x38400000
#define RTK_HWREV_8100E_SPIN2 0x38800000
+#define RTK_HWREV_8168C 0x3C000000
#define RTK_HWREV_8139 0x60000000
#define RTK_HWREV_8139A 0x70000000
#define RTK_HWREV_8139AG 0x70800000
Index: dev/mii/rgephy.c
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/rgephy.c,v
retrieving revision 1.18
diff -u -r1.18 rgephy.c
--- dev/mii/rgephy.c 26 Jan 2008 14:24:14 -0000 1.18
+++ dev/mii/rgephy.c 13 Mar 2008 14:48:36 -0000
@@ -118,7 +118,6 @@
sc->mii_phy = ma->mii_phyno;
sc->mii_pdata = mii;
sc->mii_flags = mii->mii_flags;
- sc->mii_anegticks = MII_ANEGTICKS;

sc->mii_funcs = &rgephy_funcs;

@@ -288,9 +287,19 @@
* need to restart the autonegotiation process. Read
* the BMSR twice in case it's latched.
*/
- reg = PHY_READ(sc, RTK_GMEDIASTAT);
- if ((reg & RTK_GMEDIASTAT_LINK) != 0)
- break;
+ if (sc->mii_mpd_model >= 2) {
+ /* RTL8211B(L) */
+ reg = PHY_READ(sc, RGEPHY_MII_SSR);
+ if (reg & RGEPHY_SSR_LINK) {
+ sc->mii_ticks = 0;
+ break;
+ } else {
+ reg = PHY_READ(sc, RTK_GMEDIASTAT);
+ if ((reg & RTK_GMEDIASTAT_LINK) != 0)
+ sc->mii_ticks = 0;
+ break;
+ }
+ }

/*
* Only retry autonegotiation every 5 seconds.
@@ -326,14 +335,23 @@
rgephy_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
- int bmsr, bmcr;
+ int gstat, bmsr, bmcr;
+ uint16_t ssr;

mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;

- if ((PHY_READ(sc, RTK_GMEDIASTAT) & RTK_GMEDIASTAT_LINK) != 0)
- mii->mii_media_status |= IFM_ACTIVE;
+ if (sc->mii_mpd_model>= 2) {
+ ssr = PHY_READ(sc, RGEPHY_MII_SSR);
+ if (ssr & RGEPHY_SSR_LINK)
+ mii->mii_media_status |= IFM_ACTIVE;
+ } else {
+ gstat = PHY_READ(sc, RTK_GMEDIASTAT);
+ if ((gstat & RTK_GMEDIASTAT_LINK) != 0)
+ mii->mii_media_status |= IFM_ACTIVE;
+ }

+ (void)PHY_READ(sc, RGEPHY_MII_BMSR);
bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);

@@ -354,17 +372,39 @@
}
}

- bmsr = PHY_READ(sc, RTK_GMEDIASTAT);
- if ((bmsr & RTK_GMEDIASTAT_1000MBPS) != 0)
- mii->mii_media_active |= IFM_1000_T;
- else if ((bmsr & RTK_GMEDIASTAT_100MBPS) != 0)
- mii->mii_media_active |= IFM_100_TX;
- else if ((bmsr & RTK_GMEDIASTAT_10MBPS) != 0)
- mii->mii_media_active |= IFM_10_T;
- else
- mii->mii_media_active |= IFM_NONE;
- if ((bmsr & RTK_GMEDIASTAT_FDX) != 0)
- mii->mii_media_active |= IFM_FDX;
+ if (sc->mii_mpd_model >= 2) {
+ ssr = PHY_READ(sc, RGEPHY_MII_SSR);
+ switch (ssr & RGEPHY_SSR_SPD_MASK) {
+ case RGEPHY_SSR_S1000:
+ mii->mii_media_active |= IFM_1000_T;
+ break;
+ case RGEPHY_SSR_S100:
+ mii->mii_media_active |= IFM_100_TX;
+ break;
+ case RGEPHY_SSR_S10:
+ mii->mii_media_active |= IFM_10_T;
+ break;
+ default:
+ mii->mii_media_active |= IFM_NONE;
+ break;
+ }
+ if (ssr & RGEPHY_SSR_FDX)
+ mii->mii_media_active |= IFM_FDX;
+ else
+ mii->mii_media_active |= IFM_HDX;
+ } else {
+ gstat = PHY_READ(sc, RTK_GMEDIASTAT);
+ if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0)
+ mii->mii_media_active |= IFM_1000_T;
+ else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0)
+ mii->mii_media_active |= IFM_100_TX;
+ else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0)
+ mii->mii_media_active |= IFM_10_T;
+ else
+ mii->mii_media_active |= IFM_NONE;
+ if ((gstat & RTK_GMEDIASTAT_FDX) != 0)
+ mii->mii_media_active |= IFM_FDX;
+ }
}


@@ -394,8 +434,10 @@
uint32_t bmsr;
int i;

- PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
- DELAY(1000);
+ if (sc->mii_mpd_model < 2) {
+ PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
+ DELAY(1000);
+ }

for (i = 0; i < 15000; i++) {
bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
Index: dev/mii/rgephyreg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/rgephyreg.h,v
retrieving revision 1.2
diff -u -r1.2 rgephyreg.h
--- dev/mii/rgephyreg.h 29 Nov 2006 14:01:53 -0000 1.2
+++ dev/mii/rgephyreg.h 13 Mar 2008 14:48:36 -0000
@@ -137,6 +137,17 @@
#define RGEPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
#define RGEPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */

-
+/* RTL8211B(L) */
+#define RGEPHY_MII_SSR 0x11 /* PHY Specific status register */
+#define RGEPHY_SSR_S1000 0x8000 /* 1000Mbps */
+#define RGEPHY_SSR_S100 0x4000 /* 100Mbps */
+#define RGEPHY_SSR_S10 0x0000 /* 10Mbps */
+#define RGEPHY_SSR_SPD_MASK 0xc000
+#define RGEPHY_SSR_FDX 0x2000 /* full duplex */
+#define RGEPHY_SSR_PAGE_RECEIVED 0x1000 /* new page received */
+#define RGEPHY_SSR_SPD_DPLX_RESOLVED 0x0800 /* speed/duplex resolved */
+#define RGEPHY_SSR_LINK 0x0400 /* link up */
+#define RGEPHY_SSR_MDI_XOVER 0x0040 /* MDI crossover */
+#define RGEPHY_SSR_JABBER 0x0001 /* Jabber */

#endif /* _DEV_MII_RGEPHYREG_H_ */

--
Posted automagically by a mail2news gateway at muc.de e.V.
Please direct questions, flames, donations, etc. to news-***@muc.de
Brad du Plessis
2008-03-14 07:04:38 UTC
Permalink
Hi,
Post by Izumi Tsutsui
Anyway, could you try the attached (untested) patch?
rgephy part is taken from FreeBSD, and some of values
are taken from RealTek's driver. Other changes (eeprom etc.)
are by my random guess
Thanks for your help...

I applied the patch and ran the new kernel, see below.

Brad


ifconfig:

re0: flags=8802<BROADCAST,SIMPLEX,MULTICAST> mtu 1500

capabilities=3f80<TSO4,IP4CSUM_Rx,IP4CSUM_Tx,TCP4CSUM_Rx,TCP4CSUM_Tx,UDP4CSUM_Rx,UDP4CSUM_Tx>
enabled=0
address: ff:ff:ff:ff:ff:ff
media: Ethernet none (none)


and dmesg:

NetBSD 4.0_STABLE (GENERIC.MP) #0: Fri Mar 14 08:50:21 GMT 2008
***@New_Gigabyte_G31:/usr/src/sys/arch/i386/compile/GENERIC.MP
total memory = 1013 MB
rbus: rbus_min_start set to 0x40000000
avail memory = 985 MB
timecounter: Timecounters tick every 10.000 msec
timecounter: Timecounter "i8254" frequency 1193182 Hz quality 100
BIOS32 rev. 0 found at 0xfaf00
mainbus0 (root)
cpu0 at mainbus0: apid 0 (boot processor)
cpu0: Intel Celeron (Mendocino) (686-class), 1800.08 MHz, id 0x10661
cpu0: features afebfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR>
cpu0: features afebfbff<PGE,MCA,CMOV,PAT,PSE36,CFLUSH,DS,ACPI,MMX>
cpu0: features afebfbff<FXSR,SSE,SSE2,SS,TM,SBF>
cpu0: features2 e31d<SSE3,MONITOR,DS-CPL,TM2,xTPR>
cpu0: "Intel(R) Celeron(R) CPU 430 @ 1.80GHz"
cpu0: I-cache 32 KB 64B/line 8-way, D-cache 32 KB 64B/line 8-way
cpu0: using thermal monitor 1
cpu0: calibrating local timer
cpu0: apic clock running at 199 MHz
ioapic0 at mainbus0 apid 2 (I/O APIC)
ioapic0: pa 0xfec00000, version 20, 24 pins
ioapic0: misconfigured as apic 4
ioapic0: remapped to apic 2
acpi0 at mainbus0: Advanced Configuration and Power Interface
acpi0: using Intel ACPI CA subsystem version 20060217
acpi0: X/RSDT: OemId <GBT ,GBTUACPI,42302e31>, AslId <GBTU,01010101>
acpi0: SCI interrupting at int 9
acpi0: fixed-feature power button present
timecounter: Timecounter "ACPI-Fast" frequency 3579545 Hz quality 1000
ACPI-Fast 24-bit timer
ACPI Object Type 'Processor' (0x0c) at acpi0 not configured
ACPI Object Type 'Processor' (0x0c) at acpi0 not configured
ACPI Object Type 'Processor' (0x0c) at acpi0 not configured
ACPI Object Type 'Processor' (0x0c) at acpi0 not configured
acpibut0 at acpi0 (PNP0C0C): ACPI Power Button
PNP0A03 [PCI/PCI-X Host Bridge] at acpi0 not configured
PNP0C02 [Plug and Play motherboard register resources] at acpi0 not
configured
PNP0000 [AT Interrupt Controller] at acpi0 not configured
PNP0200 [AT DMA Controller] at acpi0 not configured
attimer1 at acpi0 (PNP0100): AT Timer
attimer1: io 0x40-0x43
PNP0103 [HPET Timer] at acpi0 not configured
PNP0B00 [AT Real-Time Clock] at acpi0 not configured
pcppi1 at acpi0 (PNP0800)
pcppi1: io 0x61
pcppi1: children must have an explicit unit
midi0 at pcppi1: PC speaker (CPU-intensive output)
sysbeep0 at pcppi1
npx1 at acpi0 (PNP0C04)
npx1: io 0xf0-0xff irq 13
npx1: reported by CPUID; using exception 16
PNP0501 [16550A-compatible COM port] at acpi0 not configured
PNP0400 [Standard LPT printer port] at acpi0 not configured
pckbc1 at acpi0 (PNP0303): kbd port
pckbc1: io 0x60,0x64 irq 1
PNP0C02 [Plug and Play motherboard register resources] at acpi0 not
configured
PNP0C0F [PCI interrupt link device] at acpi0 not configured
PNP0C0F [PCI interrupt link device] at acpi0 not configured
PNP0C0F [PCI interrupt link device] at acpi0 not configured
PNP0C0F [PCI interrupt link device] at acpi0 not configured
PNP0C0F [PCI interrupt link device] at acpi0 not configured
PNP0C02 [Plug and Play motherboard register resources] at acpi0 not
configured
PNP0C01 [System Board] at acpi0 not configured
INT0800 [Intel FWH Random Number Generator] at acpi0 not configured
pcppi1: attached to attimer1
pckbd0 at pckbc1 (kbd slot)
pckbc1: using irq 1 for kbd slot
wskbd0 at pckbd0: console keyboard
pms0 at pckbc1 (aux slot)
pckbc1: unable to establish interrupt for aux slot
wsmouse0 at pms0 mux 0
pci0 at mainbus0 bus 0: configuration mode 1
pci0: i/o space, memory space enabled, rd/line, rd/mult, wr/inv ok
pchb0 at pci0 dev 0 function 0
pchb0: Intel product 0x29c0 (rev. 0x02)
vga1 at pci0 dev 2 function 0: Intel product 0x29c2 (rev. 0x02)
wsdisplay0 at vga1 kbdmux 1: console (80x25, vt100 emulation), using wskbd0
wsmux1: connecting to wsdisplay0
azalia0 at pci0 dev 27 function 0: Generic High Definition Audio Controller
azalia0: interrupting at ioapic0 pin 16 (irq 5)
azalia0: host: Intel 82801GB/GR High Definition Audio Controller (rev. 1)
azalia0: host: High Definition Audio rev. 1.0
ppb0 at pci0 dev 28 function 0: Intel 82801GB/GR PCI Express Port #1
(rev. 0x01)
pci1 at ppb0 bus 1
pci1: i/o space, memory space enabled, rd/line, wr/inv ok
ppb1 at pci0 dev 28 function 1: Intel 82801GB/GR PCI Express Port #2
(rev. 0x01)
pci2 at ppb1 bus 2
pci2: i/o space, memory space enabled, rd/line, wr/inv ok
re0 at pci2 dev 0 function 0pci_mem_find: void region
: RealTek 8168B/8111B PCIe Gigabit Ethernet (rev. 0x02)
re0: interrupting at ioapic0 pin 17 (irq 10)
re0: Unknown revision (0x7cc00000)
re0: Ethernet address ff:ff:ff:ff:ff:ff
re0: using 256 tx descriptors
ifmedia_set: no match for 0x20/0xfffffff
uhci0 at pci0 dev 29 function 0: Intel 82801GB/GR USB UHCI Controller
(rev. 0x01)
uhci0: interrupting at ioapic0 pin 23 (irq 3)
usb0 at uhci0: USB revision 1.0
uhub0 at usb0
uhub0: Intel UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub0: 2 ports with 2 removable, self powered
uhci1 at pci0 dev 29 function 1: Intel 82801GB/GR USB UHCI Controller
(rev. 0x01)
uhci1: interrupting at ioapic0 pin 19 (irq 11)
usb1 at uhci1: USB revision 1.0
uhub1 at usb1
uhub1: Intel UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub1: 2 ports with 2 removable, self powered
uhci2 at pci0 dev 29 function 2: Intel 82801GB/GR USB UHCI Controller
(rev. 0x01)
uhci2: interrupting at ioapic0 pin 18 (irq 9)
usb2 at uhci2: USB revision 1.0
uhub2 at usb2
uhub2: Intel UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub2: 2 ports with 2 removable, self powered
uhci3 at pci0 dev 29 function 3: Intel 82801GB/GR USB UHCI Controller
(rev. 0x01)
uhci3: interrupting at ioapic0 pin 16 (irq 5)
usb3 at uhci3: USB revision 1.0
uhub3 at usb3
uhub3: Intel UHCI root hub, class 9/0, rev 1.00/1.00, addr 1
uhub3: 2 ports with 2 removable, self powered
ehci0 at pci0 dev 29 function 7: Intel 82801GB/GR USB EHCI Controller
(rev. 0x01)
ehci0: interrupting at ioapic0 pin 23 (irq 3)
ehci0: BIOS has given up ownership
ehci0: EHCI version 1.0
ehci0: companion controllers, 2 ports each: uhci0 uhci1 uhci2 uhci3
usb4 at ehci0: USB revision 2.0
uhub4 at usb4
uhub4: Intel EHCI root hub, class 9/0, rev 2.00/1.00, addr 1
uhub4: 8 ports with 8 removable, self powered
ppb2 at pci0 dev 30 function 0: Intel 82801BA Hub-PCI Bridge (rev. 0xe1)
pci3 at ppb2 bus 3
pci3: i/o space, memory space enabled
rtk0 at pci3 dev 1 function 0: Realtek 8139 10/100BaseTX (rev. 0x10)
rtk0: interrupting at ioapic0 pin 19 (irq 11)
rtk0: Ethernet address 00:13:49:24:fe:8b
rlphy0 at rtk0 phy 7: Realtek internal PHY
rlphy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, auto
pcib0 at pci0 dev 31 function 0
pcib0: Intel 82801GB/GR LPC Interface Bridge (rev. 0x01)
piixide0 at pci0 dev 31 function 1
piixide0: Intel 82801GB/GR IDE Controller (ICH7) (rev. 0x01)
piixide0: bus-master DMA support present
piixide0: primary channel configured to compatibility mode
piixide0: primary channel interrupting at ioapic0 pin 14 (irq 14)
atabus0 at piixide0 channel 0
piixide0: secondary channel configured to compatibility mode
piixide0: secondary channel interrupting at ioapic0 pin 15 (irq 15)
atabus1 at piixide0 channel 1
piixide1 at pci0 dev 31 function 2
piixide1: Intel 82801GB/GR Serial ATA/Raid Controller (ICH7) (rev. 0x01)
piixide1: bus-master DMA support present
piixide1: primary channel configured to native-PCI mode
piixide1: using ioapic0 pin 19 (irq 11) for native-PCI interrupt
atabus2 at piixide1 channel 0
piixide1: secondary channel configured to native-PCI mode
atabus3 at piixide1 channel 1
Intel 82801GB/GR SMBus Controller (SMBus serial bus, revision 0x01) at
pci0 dev 31 function 3 not configured
isa0 at pcib0
lpt0 at isa0 port 0x378-0x37b irq 7
com0 at isa0 port 0x3f8-0x3ff irq 4: ns16550a, working fifo
isapnp0 at isa0 port 0x279: ISA Plug 'n Play device support
isapnp0: no ISA Plug 'n Play devices found
ioapic0: enabling
timecounter: Timecounter "clockinterrupt" frequency 100 Hz quality 0
azalia0: codec[2]: 0x10ec/0x0662 (rev. 1.1)
azalia0: codec[2]: High Definition Audio rev. 1.0
azalia0: playback: max channels=2, encodings=1<PCM>
azalia0: playback: PCM formats=e0160<24bit,20bit,16bit,96kHz,48kHz,44.1kHz>
azalia0: recording: max channels=2, encodings=1<PCM>
azalia0: recording: PCM formats=60160<20bit,16bit,96kHz,48kHz,44.1kHz>
audio0 at azalia0: full duplex, independent
Kernelized RAIDframe activated
uhidev0 at uhub2 port 1 configuration 1 interface 0
uhidev0: Microsoft Basic Optical Mouse, rev 1.10/0.00, addr 2, iclass 3/1
ums0 at uhidev0: 3 buttons and Z dir.
wsmouse1 at ums0 mux 0
wd0 at atabus2 drive 0: <WDC WD7500AAKS-00RBA0>
wd0: drive supports 16-sector PIO transfers, LBA48 addressing
wd0: 698 GB, 1453521 cyl, 16 head, 63 sec, 512 bytes/sect x 1465149168
sectors
wd0: 32-bit data port
wd0: drive supports PIO mode 4, DMA mode 2, Ultra-DMA mode 6 (Ultra/133)
wd0(piixide1:0:0): using PIO mode 4, Ultra-DMA mode 6 (Ultra/133) (using
DMA)
boot device: wd0
root on wd0a dumps on wd0b
root file system type: ffs
wsdisplay0: screen 1 added (80x25, vt100 emulation)
wsdisplay0: screen 2 added (80x25, vt100 emulation)
wsdisplay0: screen 3 added (80x25, vt100 emulation)
wsdisplay0: screen 4 added (80x25, vt100 emulation)





--
Posted automagically by a mail2news gateway at muc.de e.V.
Please direct questions, flames, donations, etc. to news-***@muc.de
Izumi Tsutsui
2008-03-14 16:08:03 UTC
Permalink
Post by Brad du Plessis
re0 at pci2 dev 0 function 0pci_mem_find: void region
: RealTek 8168B/8111B PCIe Gigabit Ethernet (rev. 0x02)
re0: interrupting at ioapic0 pin 17 (irq 10)
re0: Unknown revision (0x7cc00000)
re0: Ethernet address ff:ff:ff:ff:ff:ff
re0: using 256 tx descriptors
ifmedia_set: no match for 0x20/0xfffffff
Umm, all I/O read ops looks to return 0xffffffff,
but I don't think my patch causes such problem..
Does it always happen even after powercycle,
or only after reboot from Windows?

Anyway, could you try diffs only against rgephy.c
and rgephyreg.h first?
---
Izumi Tsutsui

--
Posted automagically by a mail2news gateway at muc.de e.V.
Please direct questions, flames, donations, etc. to news-***@muc.de
Brad du Plessis
2008-03-18 07:05:59 UTC
Permalink
Post by Izumi Tsutsui
Anyway, could you try diffs only against rgephy.c
and rgephyreg.h first?
Ok I tried this, see results below.

Thanks,
Brad

ifconfig re0:

re0: flags=8802<BROADCAST,SIMPLEX,MULTICAST> mtu 1500

capabilities=3f80<TSO4,IP4CSUM_Rx,IP4CSUM_Tx,TCP4CSUM_Rx,TCP4CSUM_Tx,UDP4CSUM_Rx,UDP4CSUM_Tx>
enabled=0
address: 00:00:00:00:00:00
media: Ethernet autoselect (none)
status: no carrier


dmesg:

--snip--
re0 at pci2 dev 0 function 0pci_mem_find: void region
: RealTek 8168B/8111B PCIe Gigabit Ethernet (rev. 0x02)
re0: interrupting at ioapic0 pin 17 (irq 10)
re0: Unknown revision (0x3c000000)
re0: Ethernet address 00:00:00:00:00:00
re0: using 256 tx descriptors
rgephy0 at re0 phy 7: RTL8169S/8110S 1000BASE-T media interface, rev. 2
rgephy0: 10baseT, 10baseT-FDX, 100baseTX, 100baseTX-FDX, 1000baseT,
1000baseT-FDX, auto
--snip--


--
Posted automagically by a mail2news gateway at muc.de e.V.
Please direct questions, flames, donations, etc. to news-***@muc.de
Izumi Tsutsui
2008-03-19 15:25:10 UTC
Permalink
Post by Brad du Plessis
Post by Izumi Tsutsui
Anyway, could you try diffs only against rgephy.c
and rgephyreg.h first?
Ok I tried this, see results below.
media: Ethernet autoselect (none)
status: no carrier
Well, there is some botch in the previous one.

Could you try this one and see if link status is up?
(all zero'ed MAC address is another problem)
---
Izumi Tsutsui


Index: rgephy.c
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/rgephy.c,v
retrieving revision 1.18
diff -u -r1.18 rgephy.c
--- rgephy.c 26 Jan 2008 14:24:14 -0000 1.18
+++ rgephy.c 19 Mar 2008 15:21:55 -0000
@@ -288,9 +288,20 @@
* need to restart the autonegotiation process. Read
* the BMSR twice in case it's latched.
*/
- reg = PHY_READ(sc, RTK_GMEDIASTAT);
- if ((reg & RTK_GMEDIASTAT_LINK) != 0)
- break;
+ if (sc->mii_mpd_model >= 2) {
+ /* RTL8211B(L) */
+ reg = PHY_READ(sc, RGEPHY_MII_SSR);
+ if (reg & RGEPHY_SSR_LINK) {
+ sc->mii_ticks = 0;
+ break;
+ }
+ } else {
+ reg = PHY_READ(sc, RTK_GMEDIASTAT);
+ if ((reg & RTK_GMEDIASTAT_LINK) != 0) {
+ sc->mii_ticks = 0;
+ break;
+ }
+ }

/*
* Only retry autonegotiation every 5 seconds.
@@ -326,15 +337,24 @@
rgephy_status(struct mii_softc *sc)
{
struct mii_data *mii = sc->mii_pdata;
- int bmsr, bmcr;
+ int gstat, bmsr, bmcr;
+ uint16_t ssr;

mii->mii_media_status = IFM_AVALID;
mii->mii_media_active = IFM_ETHER;

- if ((PHY_READ(sc, RTK_GMEDIASTAT) & RTK_GMEDIASTAT_LINK) != 0)
- mii->mii_media_status |= IFM_ACTIVE;
+ if (sc->mii_mpd_model>= 2) {
+ ssr = PHY_READ(sc, RGEPHY_MII_SSR);
+ if (ssr & RGEPHY_SSR_LINK)
+ mii->mii_media_status |= IFM_ACTIVE;
+ } else {
+ gstat = PHY_READ(sc, RTK_GMEDIASTAT);
+ if ((gstat & RTK_GMEDIASTAT_LINK) != 0)
+ mii->mii_media_status |= IFM_ACTIVE;
+ }

bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
+ bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
bmcr = PHY_READ(sc, RGEPHY_MII_BMCR);

if ((bmcr & RGEPHY_BMCR_ISO) != 0) {
@@ -354,17 +374,39 @@
}
}

- bmsr = PHY_READ(sc, RTK_GMEDIASTAT);
- if ((bmsr & RTK_GMEDIASTAT_1000MBPS) != 0)
- mii->mii_media_active |= IFM_1000_T;
- else if ((bmsr & RTK_GMEDIASTAT_100MBPS) != 0)
- mii->mii_media_active |= IFM_100_TX;
- else if ((bmsr & RTK_GMEDIASTAT_10MBPS) != 0)
- mii->mii_media_active |= IFM_10_T;
- else
- mii->mii_media_active |= IFM_NONE;
- if ((bmsr & RTK_GMEDIASTAT_FDX) != 0)
- mii->mii_media_active |= IFM_FDX;
+ if (sc->mii_mpd_model >= 2) {
+ ssr = PHY_READ(sc, RGEPHY_MII_SSR);
+ switch (ssr & RGEPHY_SSR_SPD_MASK) {
+ case RGEPHY_SSR_S1000:
+ mii->mii_media_active |= IFM_1000_T;
+ break;
+ case RGEPHY_SSR_S100:
+ mii->mii_media_active |= IFM_100_TX;
+ break;
+ case RGEPHY_SSR_S10:
+ mii->mii_media_active |= IFM_10_T;
+ break;
+ default:
+ mii->mii_media_active |= IFM_NONE;
+ break;
+ }
+ if (ssr & RGEPHY_SSR_FDX)
+ mii->mii_media_active |= IFM_FDX;
+ else
+ mii->mii_media_active |= IFM_HDX;
+ } else {
+ gstat = PHY_READ(sc, RTK_GMEDIASTAT);
+ if ((gstat & RTK_GMEDIASTAT_1000MBPS) != 0)
+ mii->mii_media_active |= IFM_1000_T;
+ else if ((gstat & RTK_GMEDIASTAT_100MBPS) != 0)
+ mii->mii_media_active |= IFM_100_TX;
+ else if ((gstat & RTK_GMEDIASTAT_10MBPS) != 0)
+ mii->mii_media_active |= IFM_10_T;
+ else
+ mii->mii_media_active |= IFM_NONE;
+ if ((gstat & RTK_GMEDIASTAT_FDX) != 0)
+ mii->mii_media_active |= IFM_FDX;
+ }
}


@@ -394,8 +436,10 @@
uint32_t bmsr;
int i;

- PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
- DELAY(1000);
+ if (sc->mii_mpd_model < 2) {
+ PHY_WRITE(sc, RGEPHY_MII_BMCR, RGEPHY_BMCR_PDOWN);
+ DELAY(1000);
+ }

for (i = 0; i < 15000; i++) {
bmsr = PHY_READ(sc, RGEPHY_MII_BMSR);
Index: rgephyreg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/rgephyreg.h,v
retrieving revision 1.2
diff -u -r1.2 rgephyreg.h
--- rgephyreg.h 29 Nov 2006 14:01:53 -0000 1.2
+++ rgephyreg.h 19 Mar 2008 15:21:55 -0000
@@ -137,6 +137,17 @@
#define RGEPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
#define RGEPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */

-
+/* RTL8211B(L) */
+#define RGEPHY_MII_SSR 0x11 /* PHY Specific status register */
+#define RGEPHY_SSR_S1000 0x8000 /* 1000Mbps */
+#define RGEPHY_SSR_S100 0x4000 /* 100Mbps */
+#define RGEPHY_SSR_S10 0x0000 /* 10Mbps */
+#define RGEPHY_SSR_SPD_MASK 0xc000
+#define RGEPHY_SSR_FDX 0x2000 /* full duplex */
+#define RGEPHY_SSR_PAGE_RECEIVED 0x1000 /* new page received */
+#define RGEPHY_SSR_SPD_DPLX_RESOLVED 0x0800 /* speed/duplex resolved */
+#define RGEPHY_SSR_LINK 0x0400 /* link up */
+#define RGEPHY_SSR_MDI_XOVER 0x0040 /* MDI crossover */
+#define RGEPHY_SSR_JABBER 0x0001 /* Jabber */

#endif /* _DEV_MII_RGEPHYREG_H_ */

--
Posted automagically by a mail2news gateway at muc.de e.V.
Please direct questions, flames, donations, etc. to news-***@muc.de
Loading...